Area Analysis for On-chip Routers with Different Data-link Widths

Compared with the traditional and inter-chip networks, on-chip networks （NoCs） have enormous wire resources which can be traded for improving other performance requirements. This means that much wider data links can be used for NoCs. This paper focuses on the area costs for on-chip routers under four different data-link widths： 8 bits, 16 bits, 128 bits, and 256bits. Firstly, a virtual-channel based on-chip router is introduced. Secondly, the components of the router are implemented by Verilog HDL models and synthesized by Quartus II 4.0 in a FPGA device. Finally, the area costs are analyzed. It can be seen from the results that data-link width has great influence on area costs of buffers and crossbar while has no influence on area costs of arbiter.     

一种低延迟低功耗的片上全局互连方法

提出了一种用于片上全局互连的混合插入方法. 该方法利用中继驱动器和低摆幅差分信号电路在驱动不同长度连线时的优点，将它们混合插入到连线的合适位置，从而降低互连的延时和功耗. 模拟结果表明，该方法与已有方法相比在延时、能耗、能耗延时积以及面积等方面都获得了一定程度的改善.     

标准数字CMOS工艺中LC谐振回路的改进和应用

提出了一种在标准数字CMOS工艺条件下,提高片上螺旋电感性能的实用方法,以及在缺少双层多晶硅电容的情况下,可以大大节约芯片面积的一种电容实现方法.介绍了这两种方法在电路设计中的一种应用,即利用0 .35 μm1P4 M标准数字CMOS工艺实现的、单片集成的L C压控振荡器.     

用CMOS工艺实现非接触IC卡天线的集成化设计

论述了用CMOS工艺实现非接触式IC卡天线的集成化需要考虑的各个方面,建立了集成天线的模型,给出了合理的设计方案,并通过实验验证了模型和设计方案.实验结果表明,采用片上天线完全可以提供非接触式IC卡工作所需要的能量.在频率为2 2 .5 MHz、感应强度为6×10 - 4 T的磁场中,面积为2 m m×2 mm的集成天线可以为10 kΩ的负载提供1.2 2 5 m W的能量.     

Experience with Applying Formal Methods to Protocol Specification and System Architecture

In the last three years or so we at Enterprise Platforms Group at Intel Corporation have been applying formal methods to various problems that arose during the process of defining platform architectures for Intel's processor families. In this paper we give an overview of some of the problems we have worked on, the results we have obtained, and the lessons we have learned. The last topic is addressed mainly from the perspective of platform architects.     

An accurate and practical buffer allocation model for the buffer cache based on marginal gains

A new dynamic buffer allocation strategy based on the notion of marginal gains is presented for the buffer cache that is used by the operating system to store frequently accessed disk blocks in main memory, and the performance of the proposed strategy is compared with those of previous allocation strategies. In the proposed strategy, marginal gain values are predicted by exploiting functions that approximate the expected number of buffer hits per unit time. Experimental results from both trace-driven simulation and an actual implementation in the FreeBSD operating system show that the proposed strategy accurately predicts the marginal gain values for various workloads resulting in significantly improved buffer hit ratios.     

二进制翻译后端指令分级索引策略

随着硬件平台的多元化,软件兼容性问题日益突出,二进制翻译技术是解决软件兼容性问题的重要手段.鉴于二进制翻译系统大部分执行时间消耗在后端指令的查找和执行过程中,高效的指令索引策略可以减少系统的指令查找开销,提高系统的整体效率.在对二进制翻译系统后端指令局部性特征进行统计分析的基础上,设计了一种能充分挖掘现代计算机系统硬件性能的二进制翻译指令分级索引策略.该策略结合二进制翻译系统后端指令特殊的局部性特征,使用针对性的替换算法对后端指令进行缓存,降低了系统的指令查找开销.在引入了LIIS索引策略后,开源二进制翻译系统QEMU的后端指令查找时间减少了70％,整个系统执行效率提高了15％.     

程序局部性的量化分析

给出与平台无关的局部性量化方法,从空间局部性和时间局部性2个角度,量化SPEC2000测试基准程序,以及这些程序的数据段、代码段和堆栈段。时间和空间局部性组成的二维局部性分布直观地展示了基准测试程序的局部性。实验结果表明,程序数据局部性主要由堆段的局部性决定,堆段的局部性最差,栈的局部性最优。     

数据缓存按需同步的设计与应用

数据缓存可以显著提高读取性能,但也需要及时同步以保证数据实时性。数据源变化触发的即时同步是一种通用的解决方案。但是大压力下,数据快速变化导致的频繁同步必然对服务器性能和通信效率产生负面影响。本文介绍的数据缓存按需同步方案根据业务需求定制同步策略,可以在满足实时性指标的基础上改善服务器性能和通信效率。该方案已经成功应用于笔者团队研发的UniBase分布式内存数据库,并在实际项目中证明了其可行性。